The semiconductor technology is heading toward higher capacity and higher performance, and techniques are being developed according to this trend. In a dynamic random access memory device (DRAM), the capacity is being greatly increased and in this situation, complicated techniques for fine structures are being developed.
In order to see into the DRAM devices which have been developed so far, a self-aligned contact (SAC) is introduced into the cell. Such a feature is disclosed in a number of references (e.g., IEDM 95 pp 907/IEDM 96 pp 597). Further, in a metallization process, the conventional polycide structure is being replaced with metal structures (IEDM 96 pp 597). That is, the metal wiring, particularly the bit lines, are being shifted from the conventional polycide structure to metal lines, thereby improving the performance of the device.
FIG. 1 is a sectional view of a conventional semiconductor memory device of the prior art.
Referring to FIG. 1, the method for fabricating this conventional semiconductor memory device will be described. First, an element isolating region 12 is formed on a semiconductor substrate 10, for defining an active region and an inactive region, and the active region comprises a cell region, a core region and a peripheral region. Then a gate electrode 14 (a conductive layer) is formed on the active region of the semiconductor substrate 10. The gate electrode 14 comprises a polysilicon layer 14a and a tungsten silicide layer 14b sequentially stacked. The upper face and the side walls of the gate electrode 14 are covered by insulating layers such as a mask insulating layer 14c and a nitride film spacer 15. These insulating layers have an etch selection ratio relative to an oxide inter-layer insulating layer.
Then high concentration impurity ions are implanted into the semiconductor substrate 10 at both side portions of the gate electrode 14 by applying a well known ion-implanting process. As a result of this process, a source/drain region is formed. In this manner, there is formed a MOS transistor which includes the gate electrode 14 and the source/drain region. An n type high concentration impurity and a p type impurity are doped into the core region, so as to form an n+ impurity region 16a and a p+ impurity region 16b. In the peripheral region, there are implanted high concentration impurity ions so as to form an n+ impurity region 16c.
Then a first insulating layer 18 is formed on the semiconductor substrate, covering the gate electrode 14. For example, the first insulating layer 18 may be a BPSG layer. Then by using a photoresist pattern as the mask, the first insulating layer 18 is etched until the source/drain regions between the gate electrodes 14 are exposed, thereby forming an open region. For example, the open region is filled with polysilicon, and thus, a bit line pad poly 20a and a storage pad poly 20b are formed.
Then a second insulating layer 22 is formed on the first insulating layer 18, covering the pad polys 20a and 20b. For example, the second insulating layer 22 may be a P-TEOS layer. Then a contact forming region is defined on the second insulating layer 22 by applying the above described process. Then by using a photoresist film pattern (not shown in the drawings) as the mask, the second insulating layer 22, the first insulating layer 18 and the mask nitride layer 14c of the gate electrode 14 are partly etched, thereby forming contact holes. Then the photoresist layer is removed.
Then the contact holes are filled with a multi-layered metal layer so as to form contact plugs 24a to 24d. For example, the multi-layered metal layer may comprise a Ti or Co layer, a CVD TiN layer and a tungsten layer (not shown in the drawings). The Ti or Co layer is for forming an ohmic layer, while the CVD TiN layer serves as a barrier for preventing the diffusion of materials.
Then a bit line forming metal layer 26a and a mask nitride layer 26b are sequentially formed on the second insulating layer 22, covering the contact plugs 24a to 24d. For example, the metal layer 26a may be tungsten (W). Then by using a bit line forming mask, the mask nitride layer 26b and the metal layer 26a are sequentially etched. In this manner, bit lines 26 are formed in the cell region. The bit lines 26 are electrically connected through the contact plugs 24a to the semiconductor substrate 10and the contact plugs 24a are electrically connected to the bit line pad poly 20a. During the formation of the bit lines 26, pads 26' for forming the wiring are formed in the core region and the peripheral region.
Then nitride film spacers 27 are formed on both of the side walls of the bit lines 26 and the pads 26'. Then a third insulating layer 28 is formed on the front face of the semiconductor substrate 10. The third insulating layer 28 is an HDP oxide layer. Then the third and second insulating layers 28 and 22 are etched by using a storage node contact forming mask, until the surface of the storage node forming pad poly 20b of the cell region is exposed, thereby forming a storage node contact hole 30. Then a polysilicon layer is formed on the third insulating layer 28, covering the contact hole 30. Then a patterning is carried out to form a lower capacitor electrode 32, i.e., a storage node. Then a capacitor is formed by applying the generally known DRAM capacitor forming process.
As described above, in the case where the wiring is formed of a metal, particularly, in the case where the DRAM bit line is composed of a metal, the metal bit forming process invites many problems due to the excessive heat released during the capacitor forming process. As can be seen in IEDM 96 pp 597, the p+ impurity region 16b which has been used to electrically connect the core region to the peripheral region comes to have a resistance of several thousand Ohm/contact. As a result, the size of the contact is reduced to 0.15 .mu.m.times.0.15 .mu.m or less. Therefore, the resistance is increased to several scores of thousands or several hundreds of thousands ohm/contact, with the result that the performance of the device is drastically deteriorated.
This is due to an absorption of the materials of the contact plugs into the silicide layer of the bottom of the contact which is formed. This contact is used to form an ohmic layer. When carrying out the finish process at a high temperature, the smaller the size of the contact, the severer the phenomenon becomes. However, the use of a metal for the bit lines 26 not only improves the performance of the device, but also the problem of the photo DOF (depth of focus margin) is bettered, as well as ameliorating the overall structural characteristics.
Then a fourth insulating layer 36 is formed on the third insulating layer 28, covering the capacitor completely. The fourth insulating layer 36 consists of a TEOS layer and a USG layer. Then by using a contact hole forming mask, the fourth and third insulating layers 36 and 28 are sequentially etched until the surface of the metal layer 26a is exposed, thereby forming contact holes. The contact holes are filled with a metal, e.g., tungsten, and thus, contacts 38a and 38b are formed for being electrically connected to the pads 26'.
Then a wiring 40 is formed on the fourth insulating layer, for being electrically connected to the contacts 38a and 38b. For example, the metal wiring 40 may be composed of aluminum (Al). More wiring may be formed on the metal wiring as shown in the drawing.